Many data processing systems receive data in a plurality of separate data streams but process the data streams together. An example of such a system is a receive antenna of a satellite payload with beamforming capability. A digital processor may receive a plurality of separate data streams from a plurality of antenna feeds and may combine and process the data streams together to form the required beams. Each data stream may be delivered to the digital processor by a separate processing chain having a separate clock signal.
In conventional systems, data sampling rates and bandwidths are sufficiently low to allow processing needs to be satisfied by means of data sampling and subsequent processing using fully synchronous design techniques. This is possible because the timing uncertainties throughout the design can be kept sufficiently small, compared to the clock period, to meet the set-up and hold needs of digital circuitry.
There is an ongoing trend towards high sampling rates. Higher sampling rates can result in the timing uncertainties between the processing chains used for different data streams being larger than a sample period. For example, at sufficiently high sampling rates, the clock signal generation within the analogue to digital converters give rise to significant timing uncertainties compared to the sampling period. Moreover, timing uncertainties may also arise in clock dividers downstream in the processing chains. Not all components of the processing chains can operate at the high sampling rates and clock dividers therefore have to be used. The clock divider start-up phase ambiguity can also give rise to significant timing uncertainties compared to the sampling period. When the combined timing uncertainty becomes large compared to the sampling period, the data streams are not provided in a sufficiently coherent manner to the digital processor and errors arise when the data streams are combined and further processed.
The invention was made in this context.